Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al,-based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
In current interconnect structures, a layer of plasma vapor deposited (PVP) TaN and a PVP Cu seed layer are used as a Cu diffusion barrier and plating seed, respectively, for advanced interconnect applications. However, with decreasing critical dimension, it is expected that the PVD-based deposition techniques will run into conformality and coverage issues. These, in turn, will lead to fill issues at plating, such as center and edge voids, which cause reliability concerns and yield degradation.
One way around this problem is to reduce the overall thickness of PVD material, and utilize a single layer of liner material which serves as both the diffusion barrier and plating seed. Another way around the aforementioned issue is the use of chemical vapor deposition (CVD) or atomic layer deposition (ALD) which result in better step coverage and conformality as compared with conventional PVP techniques. CVD or ALD ruthenium, Ru, and iridium, Ir, have the potential of replacing current PVD based barrier/plating seed for advanced interconnect application.
However, Ru and Ir are not a good metal diffusion barrier as compared with TaN, and, as such, it would be necessary to enhance the barrier resistant of the plating seed. To date, there is no known prior art that provides an interconnect structure which includes a single Ru or Ir seed layer that has enhanced barrier properties, i.e., resistant to diffusion of an interconnect conductive material such as, for example, Cu, Al, AlCu, W, Ag, and Au.